A digital counter receives a counter clock input signal and change, state, e.g., increments or decrements a digital value, in response to each cycle of the counter clock input signal. The digital value represents the number of counter clock input cycles occurring since a previous reset or load event. A digital counter can operate as a clock frequency divider by providing in response to a high frequency counter clock input a corresponding but lower frequency clock output signal.
Digital counters generally fall into two categories, ripple counters and synchronous counters. A ripple counter includes a sequence of flip-flop registers each toggling state in response to an edge-triggered, e.g., falling or rising edge, input. The first flip-flop register receives at its edge-triggered input the counter clock input signal and produces a "Q" output signal representing its state. Each successive flip-flop register receives at its input a representation of the previous register state, i.e., the Q output value of the previous register. The Q output of the last register is the output of the counter. State changes in the registers occur serially, i.e., ripple through, the counter. The counter as a whole can achieve a stable state in relation to a particular cycle of the counter clock input only after a varying delay dependent on the number of registers making a transition in response to the particular cycle of the counter clock input. In other words, the registers of a ripple counter do not all change state at a given time, but the state changes occur in a sequence rippling along from the first to the last register. A synchronous counter includes a number of flip-flop registers also responsive to a counter input clock signal and their collective state represents the number of counter clock input signal transitions since a prior reset or load event. In a synchronous counter, however, the registers are all clocked at every cycle in the counter clock input and the output state for all are concurrently valid in parallel. Thus, ripple counters and synchronous counters differ with respect to the timing of counter state validity in relation to the clock input.
Generally, either a programmable counter loads a particular number and counts up or down to zero or it counts up from zero to a particular value. In any case, the counter both loads and compares particular values which determine the frequency of the counter output in relation to the frequency of the counter clock input. To operate as a programmable counter, the contents of the counter must be read in parallel to detect a terminal state, i.e., to determine whether the counter has counted to a given value, and subsequently the counter must be loaded with a particular value.
Ripple counters have limited programmability, i.e., limited to counting according to powers of two because of the long delay needed to achieve a stable state. More particularly, delay in state transition down the sequence of registers of a ripple counter, the number of registers employed in a ripple counter, and the frequency of the counter clock input limits use of ripple counters as programmable counters. The greater the number of registers used in the sequence the greater the delay until state stability in response to the counter clock input, i.e., the greater delay in propagation of state changes along the ripple counter. For a high-speed counter clock input, the propagation delay along the ripple counter typically exceeds the counter clock input period thereby making ripple counters generally of limited value in a high-speed circuits. For applications allowing frequency divide according to only powers of two, ripple counters are acceptable frequency-divide circuits. The state of each register represents a count cycle according to a power of two and a clock output signal may be taken as the state of a selected register. However, such ripple counters typically cannot operate as general purpose programmable frequency divide circuits, i.e., capable of dividing the clock input by an arbitrary number, because there is no opportunity to read a stable counter state when the counter input clock period is less than the total propagation delay through the ripple counter.
For example, in a ten-bit ripple counter used as the programmable counter in an RF synthesizer, the total potential delay through the ten flip-flop registers could exceed the typical high frequency input clock periods of such an RF synthesizer. If, on a given input clock cycle, the counter is to toggle all ten flip-flops, then the resulting propagation delay through the entire ripple counter exceeds the input clock period and at no time is there an opportunity to read valid state data from the counter prior to the next input clock cycle.
Because synchronous counters present valid data concurrently at each register, synchronous registers are typically required when implementing a high-speed general purpose programmable counter.
Unfortunately, synchronous counters present problems with respect to power consumption in certain implementations. Power consumption for a counter becomes a concern in certain implementations, especially for a high-speed synchronous counters. In some logic families, power consumption can be optimized for certain frequencies wherein the higher the maximum allowed frequency, the greater the power requirements. In other families, e.g., CMOS, logic circuits consume power in approximate proportion to the frequency of operation. In a synchronous counter, all registers operate at the highest frequency, the frequency of the counter input clock. As a result, the power consumed by a synchronous counter is proportional to the frequency of the counter input clock times the number of registers.
A ripple counter, on the other hand, has significantly lower power consumption because registers other than the first are not necessarily clocked for each cycle in the clock input. For example, the first register in a ripple counter operates at the frequency of the input clock and its power consumption is proportional to the frequency of the input clock. The second register in a ripple counter is clocked at half this frequency consuming only one-half as much energy as the first register. For the third register, only one-quarter as much energy. Each successive register in a ripple counter consumes half as much power as the previous register. As the number of registers in a ripple counter approaches infinity, the total power consumption for the ripple counter approaches only twice that of the first register. Accordingly, ripple counters have significant advantage relative to synchronous counters with respect to power consumption especially in certain logic families, e.g., in CMOS implementations.
Thus, while ripple counters offer advantage with respect to power consumption they present disadvantage with respect to programmability. Synchronous counters are fully programmable, but present disadvantage with respect to power consumption. The circuit designer must choose between these advantages and disadvantages when implementing a counter in a high speed circuit.
Another approach used to divide or "slow down" clock speed for a portion of a programmable counter is known as variable modulous prescalar. Generally, such a counter includes a first group of flip-flops operating at the full input clock frequency which is semi-programmable, i.e., can be programmed to divide by N or to divide by (N+1). This portion of the counter is a high-speed counter using a limited number of bits and dividing by one of two preselected numbers typically separated by one. For example, the preselected numbers may be 31 and 32 or may be 15 and 16. In any case, a control line applies to this high-speed counter portion and determines which of the preselected numbers it will divide by. A second, slow-speed programmable counter portion follows and is clocked by the output of the high-speed portion. Both the high-speed counter portion and the slow-speed counter portion are traditionally synchronous counters. As a result, less high-speed circuitry is required and generally less power is consumed.
Accordingly, it would be desirable to provide a programmable high-speed counter having reduced power consumption and ability to divide an input clock by an arbitrary value. The subject matter of the present invention provides such a programmable counter.